1. Field of the Invention
The present invention relates to a numerically controlled machine for controlling a position and a moving speed of a movable shaft of a machining apparatus, and more particularly to a numerically controlled machine capable of changing acceleration and deceleration times.
2. Description of the Prior Art
There is well known, a numerically controlled machine for controlling a movable shaft of a machining apparatus by numerical values for predetermined operation. In such a numerically controlled machine, a control command is ordered as a moving amount of a movable shaft for each sampling period. An initially ordered amount is called rough interpolation data, which are data not taking the inertia of a movable part of the machine, and the output capable of being generated from driving mechanism, into consideration. Namely, there is no consideration of any of the following characteristics of the flexible part during the period of acceleration from static state to constant speed movement, and conversely during the period of deceleration from the constant speed to the static state. In such a conventional apparatus, the static state is suddenly changed to the constant speed without gradual acceleration.
However, the inertia of the movable part and the output being capable of produced by the driving mechanism are previously defined by specification of each apparatus, so that there are naturally upper limits for the speed and the acceleration that can be practically generated. Accordingly, it is necessary to produce controlling data of the accelerating and decelerating periods from the rough interpolating data. The numerically controlled apparatus generally has an accelerating and decelerating circuit for calculating controlling data of accelerating and decelerating periods which are necessary for driving a practical apparatus.
A device described in "ACCELERATING AND DECELERATING CIRCUIT" (Japanese Patent Laid-Open No. Sho 59-62909) will now be mentioned as a conventional art with reference to FIG. 1. A rough interpolator 11 generates rough interpolation data .DELTA.X for each sampling period and input them to an accelerating and decelerating circuit 17. This circuit 17 comprises n buffer registers 12 consisting of #1, #2, . . . #(n-1), #n, an adder 13, an accumulator 14 for temporarily storing the added result, a register 15 for transferring the added result, and a divider 16 for dividing the added result by n. The buffer registers #1-#n are serially connected to store the latest rough interpolation .DELTA.Xn in the buffer register #1 for each sampling period and transfer the contents of each buffer register to the buffer register of the next stage, and then input the contents .DELTA.X0 of the buffer register of the final stage to the adder 13. Accordingly, at a sampling time point, the adder performs the following calculation with the contents of the register 15 as St: EQU .DELTA.Xn-.DELTA.X0+St.fwdarw.St
to store the calculated result in the accumulator 14. The contents of the accumulator 14 are divided by n in the divider 16 and are then output as interpolation data after the accelerating/decelerating process. At the same time, the contents of the buffer registers (#1-#n) are shifted to the buffer of the next stage, .DELTA.Xn is stored in the first buffer register #1, and the contents St of the accumulator 14 is transferred to the register 15.
The aforementioned conventional apparatus is advantageous in reducing the route error during the synchronous operation of a plurality of shafts with a simple structure. Since the time constant for acceleration and deceleration is fixed, however, the time required for acceleration and deceleration would become unnecessarily long depending on the feeding speed, resulting in long driving time from starting to stopping. This is shown in FIGS. 2A-2C. In FIGS. 2A-2C, the vertical and the horizontal axis represent rough interpolation amount at each sampling time point and number of sampling times respectively.
An output waveform 1 (thick line) represents a state when an input waveform 1 (oblique line) in FIG. 2A with the number of the register buffer stages in FIG. 1 being six is input to the accelerating and decelerating circuit 17 in FIG. 1. In the conventional device, since the acceleration and deceleration have been performed at a fixed time constant regardless of the feeding speed, an output waveform 2 is obtained for the input waveform 2 shown in FIG. 2B when the feeding speed is half thereof. Here, the acceleration obtained from the output waveform 2 is a half of the output waveform 1, so that the driving system can still afford to improve its performance. At this time, if the time constant of the acceleration and deceleration can be shortened to a half, this means that the acceleration and deceleration is carried out with the same rate as in the case of the output waveform 1, resulting in the output waveform 3 for the input waveform as shown in FIG. 2C so as to reduce the driving time. In the shown example, the area of the portion surrounded by a trapezoid stands for a total moving amount, and both portions surrounded by the output waveform 2 and 3 have the same area. In other words, in the conventional device, this time difference has been wasted in vain. In machining apparatus processes, when acceleration and deceleration are frequently performed, the processing time will be greatly affected depending on whether the accelerating and decelerating time constant is fixed or varied.
To cope with such a disadvantage, it has been desired to provide a device capable of changing the time constant at the time of acceleration and deceleration. There will be considered a case in which the device shown in FIG. 1 is provided with a buffer register having a switch 5, and the number of stages of the buffer register is changed from three to two. The rough interpolation data to be input is composed of three times continued magnitude "1" as shown in FIG. 4. The divider calculates down to the first decimal place, and performs a residual process for the residual. The residual process is aimed at processing the residual generated by the 1/n dividing process by the divider and comprises the steps of: providing an accumulator and an adder separately; summing residuals at each sampling period and accumulating them in the accumulator; and adding one to the output of the divider and outputting the added result. This process realizes an accelerating/decelerating process with a high accuracy. A result of a case where no switching is performed will now be described with reference to FIG. 5. The initial values of the buffer register, the accumulator and the register are all zero.
When "1" is input at the first sampling time, "1" is stored in the buffer register #1. Meanwhile, as a result of a subtraction of the output "0" of the buffer register #3 which is the final stage of the buffer register from the sum of the input "1" and the contents "0" of the register, "1" is input to the accumulator. The divided result becomes "0.3" with a residual "0.1" so as to render an output "0.3".
At the second sampling time, the input is also "1", and the content "1" of the buffer register #1 is shifted to the buffer register #2. The input "1" is stored in the buffer register #1. As a result of subtraction of the output "0" of the buffer register #3 which is the final stage of the buffer register from the sum of the input "1" and the content "1" of the register, "2" is input to the accumulator. As a result, the quotient will become "0.6" with a residual "0.2". A carry from the total residual "0.3" (0.1+0.2") will become "0.1" which is then summed with a carry "0.1" from the quotient "0.6" and the total residual "0.1", resulting in a sum "0.7" as an output.
At the third sampling time, the input is aIso "1" and the content "1" of the buffer register #1 is shifted to the buffer register #2 while the content of the buffer register #2 is shifted to the buffer register #3. The input "1" is stored in the buffer register #1. As a result of subtraction of the output "0" of the buffer register #3 which is the final stage of the buffer register from the sum of the input "1" and the content "2" of the register, "3" is input to the accumulator. The quotient then becomes "1" with a residual "0" and an output "1".
At the fourth sampling time, the input is "0" and the content of the buffer register #2 is shifted to the buffer register #3 while the content "1" of the buffer register #1 is shifted to the buffer register #2. The input "0" is stored in the buffer register #1. As a result of the subtraction of the output "1" of the buffer register which is the final stage of the buffer register from the sum of the input "0" and the content "3" of the register, "2" is input to the accumulator. Then the quotient becomes "0.6" with a residual "0.2" and an output "0.6".
At the fifth sampling time, the input is also "0", and the content of the buffer register #2 is shifted to the buffer register #3 while the content of the buffer register #1 is shifted to the buffer register #2. The input "0" is stored in the buffer register #1. As a result of subtraction of the output "1" of the buffer register #3 being the final stage of the buffer register from the sum of the input "0" and the content "2" of the register, "1" is input to the accumulator. The quotient then becomes "0.3" with a residual "0.1", so that the total residual, summed with the previous residual "0.2", becomes "0.3". Therefore, the carry from the total residual "0.3" becomes "0.1" with an output "0.4" as a sum of the quotient "0.3" and the carry "0.1" from the residual.
At the sixth sampling time, the input is also "0", and the content of the buffer register #2 is shifted to the buffer register #3 while the content of the buffer register #1 is shifted to the buffer register #2. The input "0" is stored in the buffer register #1. As a result of subtraction of the output "1" of the buffer register #3 being the final stage of the buffer register from the sum of the input "0" and the content of the register "1", "0" is input to the accumulator. Then the divided result is "0" with a residual "0" and an output "0". Hereafter, all the outputs will be "0". Consequently, the total of the inputs and outputs are equally "3", so as to enable accurate accelerating and decelerating processes.
A case where the switching operation is carried out will now be described with reference to FIG. 6. The initial value and the input are the same as those in FIG. 5, and the number of stages of the buffer register is switched after the third sampling time. Namely, from the fourth sampling time, the output of the buffer register #2 is supplied to the accumulator while the output of the buffer register #3 is discarded. Until the third sampling time, the processes are the same as those in FIG. 5.
The number of stages is switched before the fourth sampling time. The input becomes "0" at the fourth sampling time, and the content of the buffer register #1 is shifted to the buffer register #2 while the input "0" is stored in the buffer register #1. As a subtraction of the output "1" of the buffer register #2 being a new final stage of the buffer register from the sum of the input "0" and the content "3" of the register, "2" is input to the accumulator. Thus, the quotient is "0.6" with a residual "0.2" and an output "0.6".
At the fifth sampling time, the input is also "0" and the content of the buffer register #1 is shifted to the buffer register #2. The input "0" is stored in the buffer register #1. As a result of the subtraction of the output "1" of the buffer register #2 being a new final stage of the buffer register from a sum of the input "0" and the content "2" of the register, "1" is input to the accumulator. Thus the quotient is "0.3" with a residual "0.1", so that a carry from the total residual 0.3(=0.1+0.2) becomes "0.1", rendering an output "0.4" as a sum of the quotient "0.3" and the carry from the residual "0.1".
After the fifth sampling time, the content of the buffer register always becomes "0" so as to store "1" in the accumulator, the output of "0.3" or "0.4" will continue forever. In this manner, it is impossible to perform a correct acceleration just by switching the number of stages of the buffer register.
Further a case where the content of the buffer register to be eliminated is subtracted from the accumulator is shown in FIG. 7. The initial value and the input value are the same as in FIG. 5, and the contents of the buffer register #3 and the output of the buffer register #2 are simultaneously subtracted from the accumulator at the fourth sampling time. Until the third sampling time, the processes are the same as in FIG. 5.
The number of stages of the buffer register is switched at the fourth sampling time. At the fourth sampling time, the input is "0", and the content of the buffer register #1 is shifted to the buffer register #2 while the input "0" is stored in the buffer register #1. As a result of subtraction of the output "1" of the buffer register #2 being the new final stage of the buffer register and the content "1" of the buffer register #3 to be eliminated, "1" is input to the accumulator. Then the quotient becomes "0.3" with a residual "0.1" and an output "0.3".
At the fifth sampling time, the input is also "0", and the content of the buffer register #1 is shifted to the buffer register #2 while the input "0" is stored in the buffer register #1. As a result of subtraction of the output "1" of the buffer register being the final stage of the buffer register from the sum of the input "0" and the content "1" of the register, "0" is input to the accumulator. Thus, the quotient becomes "0" with a residual "0" and an output "0".
After the fifth sampling time, the output always becomes "0". Consequently, the total of the output will be "2.3" being different from the input "3" so as to be unable to perform accurate acceleration and deceleration processes. Furthermore, as to the residual process, while the total of the residual becomes "0.6" with a carry so as to render a residual "0" in FIG. 5, a residual "0.1" remains in FIG. 7. This means that it is necessary to operate the switching time for the residual process in order to provide accurate acceleration and deceleration processes.
As has described above, the machine using the conventional acceleration and deceleration processes for changing the time constant required a series of complicated processes in one sampling period. For example, replacement of buffer registers calculation of St in number of stages having been shortened (or extended) and calculation of residuals are required during one sampling period. Therefore, the operation to switch the time constant will be significantly burdensome for the total process. If it is necessary to change several-tens or several-hundred stages, the processing burden would be so heavy that the time constant could not be changed by the conventional accelerating/decelerating method.
In the conventional acceleration and deceleration method, it has been difficult to change the acceleration and deceleration time constants to desired values at a desired timing due to the increase of the burden. As a result, the operation time could not be shortened, impeding the efficiency of the processing time from being improved.